[commit: ghc] ghc-8.0: PPC/CodeGen: fix lwa instruction generation (e7201e8)

[git at git.haskell.org]

Repository : ssh://git@git.haskell.org/ghc

On branch  : ghc-8.0
Link       : http://ghc.haskell.org/trac/ghc/changeset/e7201e86eeb0f294600ff9523f042905351efad2/ghc

>---------------------------------------------------------------

commit e7201e86eeb0f294600ff9523f042905351efad2
Author: Peter Trommler <ptrommler at acm.org>
Date:   Sat Oct 1 17:56:31 2016 -0400

    PPC/CodeGen: fix lwa instruction generation
    
    Opcode lwa is a 64-bit opcode and allows a DS-form only.  This patch
    generates lwa opcodes only when the offset is a multiple of 4.
    
    Fixes #12621
    
    Test Plan: validate
    
    Reviewers: erikd, hvr, simonmar, austin, bgamari
    
    Reviewed By: bgamari
    
    Subscribers: thomie
    
    Differential Revision: https://phabricator.haskell.org/D2547
    
    GHC Trac Issues: #12621
    
    (cherry picked from commit ce3370e06165690e79a8eb22e5229b515157e00f)


>---------------------------------------------------------------

e7201e86eeb0f294600ff9523f042905351efad2
 compiler/nativeGen/PPC/CodeGen.hs | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/compiler/nativeGen/PPC/CodeGen.hs b/compiler/nativeGen/PPC/CodeGen.hs
index 4b9a180..df76211 100644
--- a/compiler/nativeGen/PPC/CodeGen.hs
+++ b/compiler/nativeGen/PPC/CodeGen.hs
@@ -9,9 +9,8 @@
 -----------------------------------------------------------------------------
 
 -- This is a big module, but, if you pay attention to
--- (a) the sectioning, (b) the type signatures, and
--- (c) the #if blah_TARGET_ARCH} things, the
--- structure should not be too overwhelming.
+-- (a) the sectioning, and (b) the type signatures,
+-- the structure should not be too overwhelming.
 
 module PPC.CodeGen (
         cmmTopCodeGen,
@@ -471,7 +470,8 @@ getRegister' _ (CmmMachOp (MO_UU_Conv W32 W64) [CmmLoad mem _]) = do
     return (Any II64 (\dst -> addr_code `snocOL` LD II32 dst addr))
 
 getRegister' _ (CmmMachOp (MO_SS_Conv W32 W64) [CmmLoad mem _]) = do
-    Amode addr addr_code <- getAmode D mem
+    -- lwa is DS-form. See Note [Power instruction format]
+    Amode addr addr_code <- getAmode DS mem
     return (Any II64 (\dst -> addr_code `snocOL` LA II32 dst addr))
 
 getRegister' dflags (CmmMachOp mop [x]) -- unary MachOps
@@ -733,6 +733,14 @@ temporary, then do the other computation, and then use the temporary:
     ... (tmp) ...
 -}
 
+{- Note [Power instruction format]
+In some instructions the 16 bit offset must be a multiple of 4, i.e.
+the two least significant bits mus be zero. The "Power ISA" specification
+calls these instruction formats "DS-FORM" and the instructions with
+arbitrary 16 bit offsets are "D-FORM".
+
+The Power ISA specification document can be obtained from www.power.org.
+-}
 data InstrForm = D | DS
 
 getAmode :: InstrForm -> CmmExpr -> NatM Amode