[commit: ghc] master: PPC: Fix right shift by 32 bits #10870 (4bd58c1)

[git at git.haskell.org]

Repository : ssh://git@git.haskell.org/ghc

On branch  : master
Link       : http://ghc.haskell.org/trac/ghc/changeset/4bd58c179b8d0f8cf2850acb920cef8605826a2a/ghc

>---------------------------------------------------------------

commit 4bd58c179b8d0f8cf2850acb920cef8605826a2a
Author: Erik de Castro Lopo <erikd at mega-nerd.com>
Date:   Sun Sep 13 18:57:40 2015 +1000

    PPC: Fix right shift by 32 bits #10870
    
    Summary: Test included.
    
    Test Plan: Run test T10870.hs on X86/X86_64/Arm/Arm64 etc
    
    Reviewers: bgamari, nomeata, austin
    
    Subscribers: thomie
    
    Differential Revision: https://phabricator.haskell.org/D1322
    
    GHC Trac Issues: #10870


>---------------------------------------------------------------

4bd58c179b8d0f8cf2850acb920cef8605826a2a
 compiler/nativeGen/PPC/Ppr.hs                    | 21 +++++++++++++++------
 testsuite/tests/codeGen/should_run/T10870.hs     | 11 +++++++++++
 testsuite/tests/codeGen/should_run/T10870.stdout |  2 ++
 testsuite/tests/codeGen/should_run/all.T         |  1 +
 4 files changed, 29 insertions(+), 6 deletions(-)

diff --git a/compiler/nativeGen/PPC/Ppr.hs b/compiler/nativeGen/PPC/Ppr.hs
index b2bfb4e..e514779 100644
--- a/compiler/nativeGen/PPC/Ppr.hs
+++ b/compiler/nativeGen/PPC/Ppr.hs
@@ -710,6 +710,21 @@ pprInstr (EXTS fmt reg1 reg2) = hcat [
 pprInstr (NEG reg1 reg2) = pprUnary (sLit "neg") reg1 reg2
 pprInstr (NOT reg1 reg2) = pprUnary (sLit "not") reg1 reg2
 
+pprInstr (SR II32 reg1 reg2 (RIImm (ImmInt i))) | i < 0  || i > 31 =
+    -- Handle the case where we are asked to shift a 32 bit register by
+    -- less than zero or more than 31 bits. We convert this into a clear
+    -- of the destination register.
+    -- Fixes ticket http://ghc.haskell.org/trac/ghc/ticket/5900
+    pprInstr (XOR reg1 reg2 (RIReg reg2))
+
+pprInstr (SL II32 reg1 reg2 (RIImm (ImmInt i))) | i < 0  || i > 31 =
+    -- As aboce for SR, but for left shifts.
+    -- Fixes ticket http://ghc.haskell.org/trac/ghc/ticket/10870
+    pprInstr (XOR reg1 reg2 (RIReg reg2))
+
+pprInstr (SRA II32 reg1 reg2 (RIImm (ImmInt i))) | i < 0  || i > 31 =
+    pprInstr (XOR reg1 reg2 (RIReg reg2))
+
 pprInstr (SL fmt reg1 reg2 ri) =
          let op = case fmt of
                        II32 -> "slw"
@@ -717,12 +732,6 @@ pprInstr (SL fmt reg1 reg2 ri) =
                        _    -> panic "PPC.Ppr.pprInstr: shift illegal size"
          in pprLogic (sLit op) reg1 reg2 (limitShiftRI fmt ri)
 
-pprInstr (SR II32 reg1 reg2 (RIImm (ImmInt i))) | i > 31 || i < 0 =
-    -- Handle the case where we are asked to shift a 32 bit register by
-    -- less than zero or more than 31 bits. We convert this into a clear
-    -- of the destination register.
-    -- Fixes ticket http://ghc.haskell.org/trac/ghc/ticket/5900
-    pprInstr (XOR reg1 reg2 (RIReg reg2))
 pprInstr (SR fmt reg1 reg2 ri) =
          let op = case fmt of
                        II32 -> "srw"
diff --git a/testsuite/tests/codeGen/should_run/T10870.hs b/testsuite/tests/codeGen/should_run/T10870.hs
new file mode 100644
index 0000000..642ef2c
--- /dev/null
+++ b/testsuite/tests/codeGen/should_run/T10870.hs
@@ -0,0 +1,11 @@
+import Data.Bits
+import Data.Int
+import Data.Word
+
+unsafeShift32R :: (Bits a, Num a) => a -> a
+unsafeShift32R x = unsafeShiftR x 32
+
+main :: IO ()
+main = do
+    print $ map unsafeShift32R [ 123456, 0x7fffffff :: Int ]
+    print $ map unsafeShift32R [ 123456, 0xffffffff :: Word ]
diff --git a/testsuite/tests/codeGen/should_run/T10870.stdout b/testsuite/tests/codeGen/should_run/T10870.stdout
new file mode 100644
index 0000000..945f244
--- /dev/null
+++ b/testsuite/tests/codeGen/should_run/T10870.stdout
@@ -0,0 +1,2 @@
+[0,0]
+[0,0]
diff --git a/testsuite/tests/codeGen/should_run/all.T b/testsuite/tests/codeGen/should_run/all.T
index ab2ce60..13eda78 100644
--- a/testsuite/tests/codeGen/should_run/all.T
+++ b/testsuite/tests/codeGen/should_run/all.T
@@ -138,3 +138,4 @@ test('T10414', [only_ways(['threaded2']), extra_ways(['threaded2'])],
      compile_and_run, ['-feager-blackholing'])
 test('T10521', normal, compile_and_run, [''])
 test('T10521b', normal, compile_and_run, [''])
+test('T10870', normal, compile_and_run, [''])