[commit: ghc] master: nativeGen: detabify/dewhitespace SPARC/CodeGen/Base (8a8bc420)

[git at git.haskell.org]

Repository : ssh://git@git.haskell.org/ghc

On branch  : master
Link       : http://ghc.haskell.org/trac/ghc/changeset/8a8bc4202a7b43c252d9c57fe53385f6882bac79/ghc

>---------------------------------------------------------------

commit 8a8bc4202a7b43c252d9c57fe53385f6882bac79
Author: Austin Seipp <austin at well-typed.com>
Date:   Fri Jul 18 22:30:25 2014 -0500

    nativeGen: detabify/dewhitespace SPARC/CodeGen/Base
    
    Signed-off-by: Austin Seipp <austin at well-typed.com>


>---------------------------------------------------------------

8a8bc4202a7b43c252d9c57fe53385f6882bac79
 compiler/nativeGen/SPARC/CodeGen/Base.hs | 80 ++++++++++++++------------------
 1 file changed, 34 insertions(+), 46 deletions(-)

diff --git a/compiler/nativeGen/SPARC/CodeGen/Base.hs b/compiler/nativeGen/SPARC/CodeGen/Base.hs
index 45b7801..270fd69 100644
--- a/compiler/nativeGen/SPARC/CodeGen/Base.hs
+++ b/compiler/nativeGen/SPARC/CodeGen/Base.hs
@@ -1,22 +1,14 @@
-
-{-# OPTIONS_GHC -fno-warn-tabs #-}
--- The above warning supression flag is a temporary kludge.
--- While working on this module you are encouraged to remove it and
--- detab the module (please do the detabbing in a separate patch). See
---     http://ghc.haskell.org/trac/ghc/wiki/Commentary/CodingStyle#TabsvsSpaces
--- for details
-
 module SPARC.CodeGen.Base (
-	InstrBlock,
-	CondCode(..),
-	ChildCode64(..),
-	Amode(..),
+        InstrBlock,
+        CondCode(..),
+        ChildCode64(..),
+        Amode(..),
 
-	Register(..),
-	setSizeOfRegister,
+        Register(..),
+        setSizeOfRegister,
 
-	getRegisterReg,
-	mangleIndexTree
+        getRegisterReg,
+        mangleIndexTree
 )
 
 where
@@ -39,25 +31,25 @@ import OrdList
 
 --------------------------------------------------------------------------------
 -- | 'InstrBlock's are the insn sequences generated by the insn selectors.
--- 	They are really trees of insns to facilitate fast appending, where a
--- 	left-to-right traversal yields the insns in the correct	order.
+--      They are really trees of insns to facilitate fast appending, where a
+--      left-to-right traversal yields the insns in the correct order.
 --
 type InstrBlock
-	= OrdList Instr
+        = OrdList Instr
 
 
 -- | Condition codes passed up the tree.
 --
 data CondCode
-	= CondCode Bool Cond InstrBlock
+        = CondCode Bool Cond InstrBlock
 
 
 -- | a.k.a "Register64"
---	Reg is the lower 32-bit temporary which contains the result. 
---	Use getHiVRegFromLo to find the other VRegUnique.  
+--      Reg is the lower 32-bit temporary which contains the result.
+--      Use getHiVRegFromLo to find the other VRegUnique.
 --
---	Rules of this simplified insn selection game are therefore that
---	the returned Reg may be modified
+--      Rules of this simplified insn selection game are therefore that
+--      the returned Reg may be modified
 --
 data ChildCode64
    = ChildCode64
@@ -67,35 +59,35 @@ data ChildCode64
 
 -- | Holds code that references a memory address.
 data Amode
-	= Amode 
-		-- the AddrMode we can use in the instruction 
-		--	that does the real load\/store.
-		AddrMode 	
+        = Amode
+                -- the AddrMode we can use in the instruction
+                --      that does the real load\/store.
+                AddrMode
 
-		-- other setup code we have to run first before we can use the
-		--	above AddrMode.
-		InstrBlock	
+                -- other setup code we have to run first before we can use the
+                --      above AddrMode.
+                InstrBlock
 
 
 
 --------------------------------------------------------------------------------
 -- | Code to produce a result into a register.
---	If the result must go in a specific register, it comes out as Fixed.
---	Otherwise, the parent can decide which register to put it in.
+--      If the result must go in a specific register, it comes out as Fixed.
+--      Otherwise, the parent can decide which register to put it in.
 --
 data Register
-	= Fixed	Size Reg InstrBlock
-	| Any	Size (Reg -> InstrBlock)
+        = Fixed Size Reg InstrBlock
+        | Any   Size (Reg -> InstrBlock)
 
 
 -- | Change the size field in a Register.
 setSizeOfRegister
-	:: Register -> Size -> Register
+        :: Register -> Size -> Register
 
 setSizeOfRegister reg size
  = case reg of
- 	Fixed _ reg code 	-> Fixed size reg code
-	Any _ codefn     	-> Any   size codefn
+        Fixed _ reg code        -> Fixed size reg code
+        Any _ codefn            -> Any   size codefn
 
 
 --------------------------------------------------------------------------------
@@ -103,7 +95,7 @@ setSizeOfRegister reg size
 getRegisterReg :: Platform -> CmmReg -> Reg
 
 getRegisterReg _ (CmmLocal (LocalReg u pk))
-  	= RegVirtual $ mkVirtualReg u (cmmTypeSize pk)
+        = RegVirtual $ mkVirtualReg u (cmmTypeSize pk)
 
 getRegisterReg platform (CmmGlobal mid)
   = case globalRegMaybe platform mid of
@@ -118,12 +110,8 @@ getRegisterReg platform (CmmGlobal mid)
 mangleIndexTree :: DynFlags -> CmmExpr -> CmmExpr
 
 mangleIndexTree dflags (CmmRegOff reg off)
-	= CmmMachOp (MO_Add width) [CmmReg reg, CmmLit (CmmInt (fromIntegral off) width)]
-	where width = typeWidth (cmmRegType dflags reg)
+        = CmmMachOp (MO_Add width) [CmmReg reg, CmmLit (CmmInt (fromIntegral off) width)]
+        where width = typeWidth (cmmRegType dflags reg)
 
 mangleIndexTree _ _
-	= panic "SPARC.CodeGen.Base.mangleIndexTree: no match"
-
-
-
-
+        = panic "SPARC.CodeGen.Base.mangleIndexTree: no match"