[commit: ghc] simd: Add support for passing SSE vectors in registers. (085ac59)

[Geoffrey Mainland]

Repository : ssh://darcs.haskell.org//srv/darcs/ghc

On branch  : simd

http://hackage.haskell.org/trac/ghc/changeset/085ac59d51c59e8d510d803cf27902d6d040b67a

>---------------------------------------------------------------

commit 085ac59d51c59e8d510d803cf27902d6d040b67a
Author: Geoffrey Mainland <gmainlan at microsoft.com>
Date:   Wed Oct 31 15:42:01 2012 +0000

    Add support for passing SSE vectors in registers.
    
    This patch adds support for 6 XMM registers on x86-64 which overlap with the F
    and D registers and may hold 128-bit wide SIMD vectors. Because there is not a
    good way to attach type information to STG registers, we aggressively bitcast in
    the LLVM back-end.

 compiler/cmm/CmmCallConv.hs              |    4 +-
 compiler/cmm/CmmExpr.hs                  |   10 +++
 compiler/cmm/CmmMachOp.hs                |   40 ++++++----
 compiler/cmm/PprC.hs                     |    9 ++
 compiler/cmm/PprCmmExpr.hs               |    1 +
 compiler/codeGen/CgUtils.hs              |    7 ++
 compiler/codeGen/StgCmmPrim.hs           |   18 +++-
 compiler/llvmGen/LlvmCodeGen/Base.hs     |   11 ++-
 compiler/llvmGen/LlvmCodeGen/CodeGen.hs  |  121 ++++++++++++++++++++++--------
 compiler/llvmGen/LlvmCodeGen/Regs.hs     |    7 ++
 compiler/nativeGen/X86/CodeGen.hs        |   88 ++++++++++++----------
 includes/CodeGen.Platform.hs             |   26 +++++++
 includes/stg/MachRegs.h                  |   24 +++---
 includes/stg/Regs.h                      |   42 ++++++++++
 includes/stg/Types.h                     |    2 +
 utils/deriveConstants/DeriveConstants.hs |    6 ++
 16 files changed, 305 insertions(+), 111 deletions(-)


Diff suppressed because of size. To see it, use:

    git show 085ac59d51c59e8d510d803cf27902d6d040b67a