[commit: ghc] master: Tell LLVM that all vector stores and loads are potentially unaligned. (f70b6b6)

[Geoffrey Mainland]

Repository : ssh://darcs.haskell.org//srv/darcs/ghc

On branch  : master

http://hackage.haskell.org/trac/ghc/changeset/f70b6b621153cd3af8b999eac4f6fab2162befa7

>---------------------------------------------------------------

commit f70b6b621153cd3af8b999eac4f6fab2162befa7
Author: Geoffrey Mainland <gmainlan at microsoft.com>
Date:   Wed Oct 31 11:56:01 2012 +0000

    Tell LLVM that all vector stores and loads are potentially unaligned.

>---------------------------------------------------------------

 compiler/llvmGen/Llvm/PpLlvm.hs |   25 ++++++++++++++++++++++---
 1 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/compiler/llvmGen/Llvm/PpLlvm.hs b/compiler/llvmGen/Llvm/PpLlvm.hs
index 2d4be3f..a709a05 100644
--- a/compiler/llvmGen/Llvm/PpLlvm.hs
+++ b/compiler/llvmGen/Llvm/PpLlvm.hs
@@ -314,12 +314,31 @@ ppSyncOrdering SyncRelease   = text "release"
 ppSyncOrdering SyncAcqRel    = text "acq_rel"
 ppSyncOrdering SyncSeqCst    = text "seq_cst"
 
-ppLoad :: LlvmVar -> SDoc
-ppLoad var = text "load" <+> texts var
+-- XXX: On x86, vector types need to be 16-byte aligned for aligned access, but
+-- we have no way of guaranteeing that this is true with GHC (we would need to
+-- modify the layout of the stack and closures, change the storage manager,
+-- etc.). So, we blindly tell LLVM that *any* vector store or load could be
+-- unaligned. In the future we may be able to guarantee that certain vector
+-- access patterns are aligned, in which case we will need a more granular way
+-- of specifying alignment.
 
+ppLoad :: LlvmVar -> SDoc
+ppLoad var
+    | isVecPtrVar var = text "load" <+> texts var <>
+                        comma <+> text "align 1"
+    | otherwise       = text "load" <+> texts var
+  where
+    isVecPtrVar :: LlvmVar -> Bool
+    isVecPtrVar = isVector . pLower . getVarType
 
 ppStore :: LlvmVar -> LlvmVar -> SDoc
-ppStore val dst = text "store" <+> texts val <> comma <+> texts dst
+ppStore val dst
+    | isVecPtrVar dst = text "store" <+> texts val <> comma <+> texts dst <>
+                        comma <+> text "align 1"
+    | otherwise       = text "store" <+> texts val <> comma <+> texts dst
+  where
+    isVecPtrVar :: LlvmVar -> Bool
+    isVecPtrVar = isVector . pLower . getVarType
 
 
 ppCast :: LlvmCastOp -> LlvmVar -> LlvmType -> SDoc