[commit: stm] master: add Eq instances (e1cdee8)

[Simon Marlow]

Repository : ssh://darcs.haskell.org//srv/darcs/packages/stm

On branch  : master

http://hackage.haskell.org/trac/ghc/changeset/e1cdee862f4bfe332ec21ad425ecb02bd2f61568

>---------------------------------------------------------------

commit e1cdee862f4bfe332ec21ad425ecb02bd2f61568
Author: Simon Marlow <marlowsd at gmail.com>
Date:   Wed Jul 4 11:28:36 2012 +0100

    add Eq instances

>---------------------------------------------------------------

 Control/Concurrent/STM/TBQueue.hs |    3 +++
 Control/Concurrent/STM/TQueue.hs  |    3 +++
 2 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/Control/Concurrent/STM/TBQueue.hs b/Control/Concurrent/STM/TBQueue.hs
index 42b04b2..01aa742 100644
--- a/Control/Concurrent/STM/TBQueue.hs
+++ b/Control/Concurrent/STM/TBQueue.hs
@@ -52,6 +52,9 @@ data TBQueue a
              _UPK_(TVar Int)  -- CW: write capacity
              _UPK_(TVar [a])  -- W:  elements written (head is most recent)
 
+instance Eq (TBQueue a) where
+  TBQueue a _ _ _ == TBQueue b _ _ _ = a == b
+
 -- Total channel capacity remaining is CR + CW. Reads only need to
 -- access CR, writes usually need to access only CW but sometimes need
 -- CR.  So in the common case we avoid contention between CR and CW.
diff --git a/Control/Concurrent/STM/TQueue.hs b/Control/Concurrent/STM/TQueue.hs
index 4f15951..e6406a0 100644
--- a/Control/Concurrent/STM/TQueue.hs
+++ b/Control/Concurrent/STM/TQueue.hs
@@ -53,6 +53,9 @@ data TQueue a = TQueue {-# UNPACK #-} !(TVar [a])
                        {-# UNPACK #-} !(TVar [a])
   deriving Typeable
 
+instance Eq (TQueue a) where
+  TQueue a _ == TQueue b _ = a == b
+
 -- |Build and returns a new instance of 'TQueue'
 newTQueue :: STM (TQueue a)
 newTQueue = do