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<p>I've never understood why functional (and in particular
Haskell-influenced) approaches to hardware never took off. I
suspect it was political (Haskell is too academic, etc.), or
perhaps the companies using it are just quiet about it :)<br>
<br>
I think you could use monads for clock domains. Once something has
a clocked input, its output will be clocked too - it fits well
with the "lift anything unclocked to clocked, but once clocked it
is *always* clocked".<br>
</p>
<div class="moz-cite-prefix">On 10/21/18 2:59 AM, Siddharth Bhat
wrote:<br>
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cite="mid:CAPipc=3iAjw1HCHy1qxgg1bMXLSr9zafsXzijQpYHH=Et4LESA@mail.gmail.com">
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Kind of tangential, but bluespev verilog is a "Haskell inspired"
version of verilog that has a strong Haskell flavour (typeclasses,
purity, a rudimentary effect system that tracks combinational
versus state based logic, clock domains embedded into the type,
width polymorphic functions, etc).
<div><br>
</div>
<div>It's a really great way to see what a haskell-like-hardware
description language could look like :)</div>
<div><br>
</div>
<div>Cheers</div>
<div>siddharth<br>
<br>
<div class="gmail_quote">
<div dir="ltr">On Sun 21 Oct, 2018, 12:34 Joachim Durchholz,
<<a href="mailto:jo@durchholz.org" moz-do-not-send="true">jo@durchholz.org</a>>
wrote:<br>
</div>
<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex">Am
21.10.18 um 04:52 schrieb Will Yager:<br>
> <br>
> This is the basis of projects like Clash (Haskell to
HDLs). I imagine one could extend the clash approach to
generate allocation-free assembly from the same (large)
subset of Haskell.<br>
<br>
Is that subset described somewhere?<br>
<br>
Regards,<br>
Jo<br>
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-- <br>
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<div dir="ltr">Sending this from my phone, please excuse any
typos!</div>
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