[GHC] #14251: LLVM Code Gen messes up registers

[GHC]

#14251: LLVM Code Gen messes up registers
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        Reporter:  angerman          |                Owner:  kavon
            Type:  bug               |               Status:  new
        Priority:  highest           |            Milestone:  8.6.1
       Component:  Compiler (LLVM)   |              Version:  8.3
      Resolution:                    |             Keywords:
Operating System:  Unknown/Multiple  |         Architecture:
 Type of failure:  Incorrect result  |  Unknown/Multiple
  at runtime                         |            Test Case:
      Blocked By:                    |             Blocking:
 Related Tickets:                    |  Differential Rev(s):
       Wiki Page:                    |
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Changes (by kavon):

 * owner:  (none) => kavon


Comment:

 I'll polish up solution (2) ASAP. Sorry I missed this!

 While it seems ugly to add `FloatReg` as padding, it we need ''something''
 to "eat up" a floating point register, since they're assigned left-to-
 right. We know Float and Double are passed in the same register on x86-64
 so it should be fine. I need to look into ARM and other calling
 conventions to make this correct on other systems.

-- 
Ticket URL: <http://ghc.haskell.org/trac/ghc/ticket/14251#comment:14>
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