[GHC] #8033: add AVX register support to llvm calling convention

[GHC]

#8033: add AVX register support to llvm calling convention
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        Reporter:  carter            |                Owner:  (none)
            Type:  task              |               Status:  new
        Priority:  normal            |            Milestone:
       Component:  Compiler          |              Version:  7.7
      Resolution:                    |             Keywords:  SIMD
Operating System:  Unknown/Multiple  |         Architecture:
                                     |  Unknown/Multiple
 Type of failure:  None/Unknown      |            Test Case:
      Blocked By:                    |             Blocking:
 Related Tickets:                    |  Differential Rev(s):
       Wiki Page:                    |
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Comment (by bgamari):

 In the interest of unsticking this, I'm going to submit this patch
 upstream to LLVM tomorrow if there is no objection,
 {{{#!patch
 diff --git a/lib/Target/X86/X86CallingConv.td
 b/lib/Target/X86/X86CallingConv.td
 index 7d146d050a5..cb6ed24a155 100644
 --- a/lib/Target/X86/X86CallingConv.td
 +++ b/lib/Target/X86/X86CallingConv.td
 @@ -650,8 +650,16 @@ def CC_X86_64_GHC : CallingConv<[

    // Pass in STG registers: F1, F2, F3, F4, D1, D2
    CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
 -            CCIfSubtarget<"hasSSE1()",
 -            CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>
 +           CCIfSubtarget<"hasSSE1()",
 +           CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>,
 +  // AVX
 +  CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
 +           CCIfSubtarget<"hasAVX()",
 +           CCAssignToReg<[YMM1, YMM2, YMM3, YMM4, YMM5, YMM6]>>>,
 +  // AVX-512
 +  CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
 +           CCIfSubtarget<"hasAVX512()",
 +           CCAssignToReg<[ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6]>>>
  ]>;

  def CC_X86_64_HiPE : CallingConv<[
 }}}

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Ticket URL: <http://ghc.haskell.org/trac/ghc/ticket/8033#comment:32>
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