[GHC] #8033: add AVX register support to llvm calling convention

[GHC]

#8033: add AVX register support to llvm calling convention
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        Reporter:  carter            |            Owner:  carter
            Type:  task              |           Status:  new
        Priority:  normal            |        Milestone:
       Component:  Compiler          |          Version:  7.7
      Resolution:                    |         Keywords:
Operating System:  Unknown/Multiple  |     Architecture:  Unknown/Multiple
 Type of failure:  None/Unknown      |       Difficulty:  Unknown
       Test Case:                    |       Blocked By:
        Blocking:                    |  Related Tickets:
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Comment (by carter):

 So does this mean that the version LLVM has is currently buggy?
 https://github.com/llvm-
 mirror/llvm/blob/master/lib/Target/X86/X86CallingConv.td#L289
 (Note that a number of other conventions seem to use )

 it uses the "hasSSE1()" check currently.

 That said, most of the useful SSE features / simd capabilities don't
 happen till sse2... so not terribly useful for us

 strictly speaking, it is correct, in SSE1 there are XMM0-7, though the
 only simd operations available then are for Floats.
 SSE2 gets the Word + Double simd primops.

 Likewise XMM8-15 start being available in sse3

 sse2 started being in intel and amd chips 2001-2003, and sse3 landed in
 2004.

-- 
Ticket URL: <http://ghc.haskell.org/trac/ghc/ticket/8033#comment:20>
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