STG register mapping

[DashiellWill]

Hi all,


I'm newbie at GHC, trying to read the source code and understand the design of GHC. 
Now I'm learning about the Haskell Execution Model, but now I'm a bit confused about the STG-machine Registers.


First, as shown in the GHC wiki e.g. https://gitlab.haskell.org/ghc/ghc/-/wikis/commentary/rts/haskell-execution/registers ,
the STG-machine has some virtual registers that are mapped to real registers, such as Base, Sp, SpLim, Hp, Rn, Fn and Dn,
but unfortunately the mapping logic of the STG registers is not explained in detail here.


Then I tried to read the source files of various platforms in rts/include/stg/MachRegs.
At first I thought they were mapped using the callee saved registers, such as aarch64, ppc, loongarch64 and riscv64 platforms,
but this seems broken on s390x and x86_64 platforms.


so now I have two questions:
1. What determines the amounts of Rn, Fn and Dn for different platforms? 
As for Rn, aarch64 has 6 registers, loongarch64 has 5 registers, ppc has 10 registers, and riscv64 has 7 registers.
As for Fn, both aarch64 and loongarch64 have 4 registers, and both ppc and riscv64 have 6 registers.


2. What is the basic rule to assign the actual processor registers to the STG machine registers?
The aarch64, loongarch64, ppc and riscv64 platforms seem to have a 'normal' mapping,
while the s390x and x86_64 platforms have an 'non-normal' mapping e.g. R4~R8, F5~F6 and D5~D6 in s390x use the caller saved registers.
Does this mean that the caller saved registers for passing argument can be used for mapping when the callee saved registers are insufficient?


Thanks,
Dashiell
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