[commit: ghc] ghc-7.10: PPC: Fix right shift by 32 bits #10870 (554cebe)

[git at git.haskell.org]

Repository : ssh://git@git.haskell.org/ghc

On branch  : ghc-7.10
Link       : http://ghc.haskell.org/trac/ghc/changeset/554cebe4b49f98ccc5ed1c264ce25852241d4c14/ghc

>---------------------------------------------------------------

commit 554cebe4b49f98ccc5ed1c264ce25852241d4c14
Author: Erik de Castro Lopo <erikd at mega-nerd.com>
Date:   Mon Oct 19 21:00:06 2015 +1100

    PPC: Fix right shift by 32 bits #10870
    
    Backported from:
    
        commit 4bd58c179b8d0f8cf2850acb920cef8605826a2a
        Author: Erik de Castro Lopo <erikd at mega-nerd.com>
        Date:   Sun Sep 13 18:57:40 2015 +1000
    
        PPC: Fix right shift by 32 bits #10870
    
    The patch in HEAD didn't apply cleanly because of the powerpc64el
    work that has been done in HEAD.


>---------------------------------------------------------------

554cebe4b49f98ccc5ed1c264ce25852241d4c14
 compiler/nativeGen/PPC/Ppr.hs | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/compiler/nativeGen/PPC/Ppr.hs b/compiler/nativeGen/PPC/Ppr.hs
index 311d256..4ae32c9 100644
--- a/compiler/nativeGen/PPC/Ppr.hs
+++ b/compiler/nativeGen/PPC/Ppr.hs
@@ -624,14 +624,22 @@ pprInstr (EXTS sz reg1 reg2) = hcat [
 pprInstr (NEG reg1 reg2) = pprUnary (sLit "neg") reg1 reg2
 pprInstr (NOT reg1 reg2) = pprUnary (sLit "not") reg1 reg2
 
-pprInstr (SLW reg1 reg2 ri) = pprLogic (sLit "slw") reg1 reg2 (limitShiftRI ri)
 
-pprInstr (SRW reg1 reg2 (RIImm (ImmInt i))) | i > 31 || i < 0 =
+pprInstr (SRW reg1 reg2 (RIImm (ImmInt i))) | i < 0  || i > 31 =
     -- Handle the case where we are asked to shift a 32 bit register by
     -- less than zero or more than 31 bits. We convert this into a clear
     -- of the destination register.
     -- Fixes ticket http://ghc.haskell.org/trac/ghc/ticket/5900
     pprInstr (XOR reg1 reg2 (RIReg reg2))
+
+pprInstr (SLW reg1 reg2 (RIImm (ImmInt i))) | i < 0  || i > 31 =
+    -- As aboce for SR, but for left shifts.
+    -- Fixes ticket http://ghc.haskell.org/trac/ghc/ticket/10870
+    pprInstr (XOR reg1 reg2 (RIReg reg2))
+
+
+pprInstr (SLW reg1 reg2 ri) = pprLogic (sLit "slw") reg1 reg2 (limitShiftRI ri)
+
 pprInstr (SRW reg1 reg2 ri) = pprLogic (sLit "srw") reg1 reg2 (limitShiftRI ri)
 
 pprInstr (SRAW reg1 reg2 ri) = pprLogic (sLit "sraw") reg1 reg2 (limitShiftRI ri)