[commit: ghc] ghc-7.10: PPC nativeGen: fix shift right arithmetic > 31 bit (9c8e7f8)

[git at git.haskell.org]

Repository : ssh://git@git.haskell.org/ghc

On branch  : ghc-7.10
Link       : http://ghc.haskell.org/trac/ghc/changeset/9c8e7f81f250f4977013d7f16e853c4b75ac97d9/ghc

>---------------------------------------------------------------

commit 9c8e7f81f250f4977013d7f16e853c4b75ac97d9
Author: Peter Trommler <ptrommler at acm.org>
Date:   Mon Nov 9 15:59:36 2015 +0100

    PPC nativeGen: fix shift right arithmetic > 31 bit
    
    Arithmetic shift right of more than 31 bits yields
    zero for positive Int and -1 for negative Int. On
    PowerPC immediates greater than 31 are not allowed,
    so replace with a shift by 31 bits which gives the
    correct result.
    
    Fixes #10870


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9c8e7f81f250f4977013d7f16e853c4b75ac97d9
 compiler/nativeGen/PPC/Ppr.hs | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/compiler/nativeGen/PPC/Ppr.hs b/compiler/nativeGen/PPC/Ppr.hs
index 4ae32c9..876b11b 100644
--- a/compiler/nativeGen/PPC/Ppr.hs
+++ b/compiler/nativeGen/PPC/Ppr.hs
@@ -637,6 +637,8 @@ pprInstr (SLW reg1 reg2 (RIImm (ImmInt i))) | i < 0  || i > 31 =
     -- Fixes ticket http://ghc.haskell.org/trac/ghc/ticket/10870
     pprInstr (XOR reg1 reg2 (RIReg reg2))
 
+pprInstr (SRAW reg1 reg2 (RIImm (ImmInt i))) | i > 31 =
+    pprInstr (SRAW reg1 reg2 (RIImm (ImmInt 31)))
 
 pprInstr (SLW reg1 reg2 ri) = pprLogic (sLit "slw") reg1 reg2 (limitShiftRI ri)