[commit: ghc] ghc-7.10: includes/stg/SMP.h: implement simple load_/store_load_barrier on armv6 and older (b41e4be)

[git at git.haskell.org]

Repository : ssh://git@git.haskell.org/ghc

On branch  : ghc-7.10
Link       : http://ghc.haskell.org/trac/ghc/changeset/b41e4be724c02c7f08821c2fd74a33c6ed1021ae/ghc

>---------------------------------------------------------------

commit b41e4be724c02c7f08821c2fd74a33c6ed1021ae
Author: Sergei Trofimovich <siarheit at google.com>
Date:   Mon May 18 22:22:18 2015 +0100

    includes/stg/SMP.h: implement simple load_/store_load_barrier on armv6 and older
    
    Assuming there is no real SMP systems on these CPUs
    I've added only compiler barrier (otherwise write_barrier
    and friends need to be fixed as well).
    
    Patch also fixes build breakage reported in #10244.
    
    Signed-off-by: Sergei Trofimovich <siarheit at google.com>
    
    Reviewers: rwbarton, nomeata, austin
    
    Reviewed By: nomeata, austin
    
    Subscribers: bgamari, thomie
    
    Differential Revision: https://phabricator.haskell.org/D894
    
    GHC Trac Issues: #10244
    
    (cherry picked from commit eaaa38ba24d5152623cb202a98f71ed09deef0bb)


>---------------------------------------------------------------

b41e4be724c02c7f08821c2fd74a33c6ed1021ae
 includes/stg/SMP.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/includes/stg/SMP.h b/includes/stg/SMP.h
index 5ded05d..5460a2b 100644
--- a/includes/stg/SMP.h
+++ b/includes/stg/SMP.h
@@ -373,6 +373,8 @@ store_load_barrier(void) {
     __asm__ __volatile__ ("sync" : : : "memory");
 #elif sparc_HOST_ARCH
     __asm__ __volatile__ ("membar #StoreLoad" : : : "memory");
+#elif arm_HOST_ARCH && defined(arm_HOST_ARCH_PRE_ARMv7)
+    __asm__ __volatile__ ("" : : : "memory");
 #elif arm_HOST_ARCH && !defined(arm_HOST_ARCH_PRE_ARMv7)
     __asm__ __volatile__ ("dmb" : : : "memory");
 #elif aarch64_HOST_ARCH
@@ -395,6 +397,8 @@ load_load_barrier(void) {
 #elif sparc_HOST_ARCH
     /* Sparc in TSO mode does not require load/load barriers. */
     __asm__ __volatile__ ("" : : : "memory");
+#elif arm_HOST_ARCH && defined(arm_HOST_ARCH_PRE_ARMv7)
+    __asm__ __volatile__ ("" : : : "memory");
 #elif arm_HOST_ARCH && !defined(arm_HOST_ARCH_PRE_ARMv7)
     __asm__ __volatile__ ("dmb" : : : "memory");
 #elif aarch64_HOST_ARCH