[commit: ghc] master: rts: Fix aarch64 implementation of xchg (f6ca695)

[git at git.haskell.org]

Repository : ssh://git@git.haskell.org/ghc

On branch  : master
Link       : http://ghc.haskell.org/trac/ghc/changeset/f6ca6959e54ede0b28735ab7e011c16b3cb172db/ghc

>---------------------------------------------------------------

commit f6ca6959e54ede0b28735ab7e011c16b3cb172db
Author: Erik de Castro Lopo <erikd at mega-nerd.com>
Date:   Thu May 28 02:57:28 2015 +0000

    rts: Fix aarch64 implementation of xchg
    
    In the previous implementation, the `stlxr` instruction clobbered
    the value that was supposed to be returned by the the `xchg`
    function.
    
    Signed-off-by: Erik de Castro Lopo <erikd at mega-nerd.com>
    
    Test Plan: build on aarch64
    
    Reviewers: austin, bgamari, rwbarton
    
    Subscribers: bgamari, thomie
    
    Differential Revision: https://phabricator.haskell.org/D932


>---------------------------------------------------------------

f6ca6959e54ede0b28735ab7e011c16b3cb172db
 includes/stg/SMP.h | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/includes/stg/SMP.h b/includes/stg/SMP.h
index 10ef83e..fbc8bdc 100644
--- a/includes/stg/SMP.h
+++ b/includes/stg/SMP.h
@@ -158,13 +158,11 @@ xchg(StgPtr p, StgWord w)
                           : "memory"
                           );
 #elif aarch64_HOST_ARCH
-    // Don't think we actually use tmp here, but leaving
-    // it for consistent numbering
     StgWord tmp; 
     __asm__ __volatile__ (
                           "1:    ldaxr  %0, [%3]\n"
-                          "      stlxr  %w0, %2, [%3]\n"
-                          "      cbnz   %w0, 1b\n"
+                          "      stlxr  %w1, %2, [%3]\n"
+                          "      cbnz   %w1, 1b\n"
                           "      dmb sy\n"
                           : "=&r" (result), "=&r" (tmp)
                           : "r" (w), "r" (p)